SCHEDULE: NOV 10-16, 2007

Evaluating the Role of Scratchpad Memories in Multi-core for Sparse Matrix Computations

Session: Posters Reception

Event Type: Poster

Time: 5:15pm - 7:00pm

Session Chair: Tamara K Grimmett

Author(s): Aditya Yanamandra, Bryan Cover, Konrad Malkowski, Padma Raghavan, Mahmut Kandemir, Mary J. Irwin

Location: Ballroom Lobby

Abstract:
We consider hardware acceleration for sparse matrix vector multiplication (SpMV), a kernel that is used widely in iterative linear solvers, modeling and simulation applications. In particular, we consider how scratchpad memory can be used for increasing the performance and the energy efficiency of SpMV in a multi-core system. Scratchpad memories (SPM) are more energy efficient than traditional caches. This, coupled with the predictability of data presence, makes SPM an attractive alternative to a cache.

We ensure the efficient utilization of the SPM by using it to store data which doesn’t perform well in the traditional cache. We evaluate the impact of using an SPM at all levels of the on-chip memory hierarchy. Depending on the level of the hierarchy in which the SPM is utilized, we observe on an eight core system an average increase in performance of 13.5%-15% at an average decrease in energy consumption of 23%-28%.

Chair/Author Details:

Tamara K Grimmett (Chair)
INL

Aditya Yanamandra
Pennsylvania State University

Bryan Cover
Pennsylvania State University

Konrad Malkowski
Pennsylvania State University

Padma Raghavan
Pennsylvania State University

Mahmut Kandemir
Pennsylvania State University

Mary J. Irwin
Pennsylvania State University

Home | About | Contact Us | Registration